1. Field of the Invention
The present invention relates to a capacitor mounting structure useful for a reduction in equivalent series inductance, a capacitor-mounted board formed by arranging capacitor mounting structures of the above type in parallel, and a wiring board on which capacitors are to be mounted.
2. Description of the Related Art
FIG. 1A is a perspective view showing a monolithic ceramic capacitor (hereinafter simply referred to as a “capacitor”) C, and FIG. 1B is a longitudinal sectional view showing the capacitor C shown in FIG. 1A.
The overall form of the capacitor C in FIG. 1A is a parallelepiped rectangle. The length L, width W, and thickness T of the capacitor C have the relationshipL>W=Twhen the length L, the width W, and the thickness T are standard values. The sizes of capacitors of the above type are given common names, such as “0603”, “1005”, etc. For example, a capacitor C called “0603” has a standard length L of 0.6 mm and a standard width W and thickness T of 0.3 mm.
This capacitor C consists of a parallelepiped ceramic chip Ca having a relationship represented by L>W=T (when L, W, and T are standard values), a large number of internal electrodes Cb which are embedded at regular intervals in the thickness direction and whose edges in the length direction are alternately exposed on opposite side surfaces in the length direction of the ceramic chip Ca, and external electrodes Cc which cover the opposite side surfaces in the length direction of the ceramic chip Ca and their peripheries, and which are formed by a single or plural layers in conduction to the exposed ends of the internal electrodes Cb.
The capacitor C serves an important role as a noise suppressing component in various electronic circuits. For example, around a large-scale integrated circuit (LSI) such as a central processing unit (CPU), a plurality of bypass capacitors are mounted in order to achieve stable operation by eliminating noise caused by power-supply switching, etc.
The capacitor C is treated as a component having a predetermined capacitance. An equivalent circuit of a capacitor has frequency characteristics similar to those of a series resonant circuit because the equivalent circuit has not only a capacitance but also an equivalent series inductance (hereinafter referred to as an “ESL”) and an equivalent series resistance (hereinafter referred to as an “ESR”).
In other words, as shown in the capacitor mounting structure shown in FIG. 2, when considering a state in which one external electrode Cc is connected to a signal electrode 12 on a board 11 and in which a current flows in the direction indicated by the broken line arrow in a capacitor C connected to the other external electrode Cc, it is difficult for a frequency range where the current frequency is lower than a resonant frequency to be affected by an ESL, and a frequency range where the current frequency is higher than the resonant frequency is easily affected by the ESL. Thus, the impedance increases substantially in proportion to an increase in frequency.
To improve the above frequency characteristics, the resonant frequency must be increased by reducing the capacitance, or the ESL must be reduced. However, a reduction in capacitance increases the impedance, so that the desired aim of noise elimination cannot be achieved. Accordingly, recently, methods in which the ESL is reduced by improving the arrangement of capacitors have been proposed.
FIG. 3 shows a capacitor mounting structure illustrating one example (see, for example, Japanese Unexamined Patent Application Publication No. 2001-23849) of the above methods. This structure includes a board 21, a circular signal electrode 22, a ring ground electrode 23 provided around the signal electrode 22, and a total of four capacitors C. The four capacitors C are disposed in a cross form. One external electrode Cc of each capacitor C is connected to the signal electrode 22, and the other signal electrode Cc thereof is connected to the ground electrode 23.
In this capacitor mounting structure, current flows in the same direction (indicated by the broken line arrow shown in FIG. 3) in each of the capacitors C disposed in the cross form, and the current vectors of each pair of two adjacent capacitors C have an angle of 90 degrees therebetween. This minimizes the mutual inductance which can be generated between each pair of adjacent capacitors C, thus reducing the ESL of the entire mounting structure.
With demands for improvements in function and performance of electronic devices such as personal computers and cellular phones, there are still strongly demands for internal electronic circuits with high packaging density. In addition, in the case of electronic circuits that treat various signal systems, such as LSIs used as CPUs, a large number of capacitors must be mounted in accordance with the signal systems.
However, in the capacitor mounting structure shown in FIG. 3, two adjacent capacitors C, which form each pair, have a sector-form dead-space region since the ground electrode 23 is circular and the four capacitors C are arranged in the cross form. In other words, in the case of arranging in parallel capacitor mounting structures of the type shown in FIG. 3 in order to mount many capacitors C, the dead space increases as the number of capacitor mounting structures increases, so that an increase in the area required for mounting cannot satisfy demands for increased packaging density.